Silanna Feature-Rich DSPs

Silanna Feature-Rich DSPs

Silanna Semiconductor introduces a feature-rich Digital Signal Processor (DSP) to its Plural™ family of high-speed, low-power Analog-to-Digital Converters (ADCs).

This integration brings advanced DSP capabilities such as digital down conversion (DDC), decimation, IQ phase correction, and gain/offset correction directly into the ADC platform,

allowing signal processing to occur at the earliest stage in the signal chain. This enables band-pass signals to be converted, filtered, and optimized internally, streamlining the processing workflow and improving the overall system efficiency.

Key DSP Benefits

• Reduced FPGA load: Offloads processing from the FPGA into the ADC
• Lower data rates: Decimation reduces bandwidth early in the signal chain
• Improved signal integrity: Digital correction compensates for IQ imbalance, gain, and offset errors
• Simplified architectures: Fewer external DSP blocks and cleaner system design
• Enhanced performance: Techniques like decimation and averaging improve effective SNR
• Faster development cycles: Integrated functionality reduces design complexity and time-to-market
• Significant reduction in unit cost : 30% reduction @ 1ku vs legacy suppliers

The Plural-DSP family includes devices with 12-, 14-, and 16-bit resolutions, supporting sampling rates from 5 to 250 MSPS. These ADCs are intended for signal-chain and test-and-measurement applications across industrial, military, medical, and communications sectors.

Devices are available in multiple package sizes, from 5×5 mm to 9×9 mm, with feature-rich variants also provided in a compact 3.4mm x 3.4mm package.

The product line supports extended temperature ranges, now available from -55°C to +125°C. The DSP Plural ADC product family and EVKs are available now.

For more information or any question, please contact:

Sivan Bahar
Mobile: +972-547710958
Email: sivan@crg.co.il